1. Field of the Invention
The present invention relates to an analog electronic timepiece, and particularly to a stable operation of an oscillation circuit at the time of driving a motor.
2. Background Art
FIG. 5 is a general block diagram of an analog electronic timepiece using a crystal oscillation circuit used in a wrist watch or the like.
The analog electronic timepiece is comprised of a semiconductor device 70, a battery 71, a crystal vibrator 72, and a motor 73. The semiconductor device 70 is comprised of an oscillation circuit 702 which enables oscillation at a stable frequency by a combination with the external crystal vibrator 72, a frequency division circuit 703 which divides a reference clock signal OSC obtained from the oscillation circuit 702 into clock signals each having a desired frequency, a constant voltage circuit 701 which drives the oscillation circuit 702 and the frequency division circuit 703, and an output control circuit 704 which drives the motor 73.
A circuit example of the related art constant voltage circuit 701 is illustrated in FIG. 6. The constant voltage circuit 701 is equipped with a reference voltage circuit 22 which generates a reference voltage Vref, a differential amplifier circuit 23, an output transistor 10, a feedback circuit 21, a voltage holding circuit 40 comprised of a capacitor, and a switch circuit 50.
The constant voltage circuit 701 has the voltage holding circuit 40 which holds a gate voltage V1 of the output transistor 10 and reduces power consumption by allowing the differential amplifier circuit 23 or the like to be intermittently operated. The differential amplifier circuit 23 and the feedback circuit 21 are stopped from operating by a signal Φ1 to turn off the switch circuit 50. At this time, the voltage holding circuit 40 holds a voltage prior to turning off of the switch circuit 50 as the gate voltage V1 of the output transistor 10. The constant voltage circuit 701 is capable of outputting a constant voltage VREG unless a load current fluctuates greatly (refer to, for example, Patent Document 1).
A block diagram of the related art oscillation circuit 702 is illustrated in FIG. 7. The oscillation circuit 702 is equipped with an oscillation inverter comprised of a PMOS transistor P01 and an NMOS transistor N01, a feedback resistor RF configured by connecting a PMOS transistor P02 and an NMOS transistor N02 in parallel, oscillation capacitors CG and CD, a coupling capacitor CC, a switch element SW comprised of a transmission gate configured of a PMOS transistor P03 and an NMOS transistor N03, a dumping resistor RD comprised of an NMOS transistor NR1 doped with a high concentration impurity under a gate thereof, and a waveform shaping circuit 100. Further, an ESD protection element ESD1 comprised of an NMOS transistor N04 and an ESD protection element ESD2 comprised of an NMOS transistor N05 are respectively provided at terminals XIN and XOUT to which the crystal vibrator 72 is connected. The NMOS transistors N02, N03, N04, N05, and NR1 are provided relative to a substrate connected to a negative electrode terminal VSS of the battery 71.
Now consider where in the analog electronic timepiece, the output control circuit 704 outputs a motor pulse output to rotate the motor 73. Since the battery 71 and the motor 73 have resistive components, a battery voltage VSS is lowered by a voltage determined by the product of the load current of the motor 73 and the internal resistance of the battery 71. With this voltage drop, a transient voltage drop occurs even in the output voltage VREG of the constant voltage circuit 701. In order to reduce current consumption of each of the oscillation circuit 702 and the frequency division circuit 703, the output voltage VREG is set to be as close to an oscillation stop voltage VDOS of the oscillation circuit 702 as possible. When the output voltage VREG falls below the oscillation stop voltage VDOS due to the voltage drop, the oscillation becomes unstable and in the worst case, the oscillation stops.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-298523